IR Drop is Signal Integrity
(SI) effect caused by wire resistance and current drawn off from Power (Vdd)
and Ground (Vss) grids. According to Ohm’s law, V = IR. If wire resistance is
too high or the current passing through the metal layers is larger than predicted,
an unacceptable Voltage drop may occur. Due to this unacceptable voltage drop,
The power supply voltage decreases. That means the required power across the
design is not reaching the cells. This results in increased noise
susceptibility and poor performance.
The design may
have different types of gates with different voltage levels. As the voltage at
gates decreased due to an unacceptable voltage drop in the supply voltage, the
gate delays are increased non-linearly. This may lead to setup time and hold
time violations depending on which path these gates are residing in the design.
As the technology node shrinks, there is a decrease in the geometries of the metal layers, and the resistance of these wires increases, leading to a decrease in power supply voltage. During Clock Tree Synthesis, the buffers and inverters are added along the clock path to balance the skew. The voltage drop on the buffers and inverters of the clock path will cause a delay in the arrival of the clock signal, resulting hold violation.
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